The iPhone 18’s A20 chip again reported to use next-gen RAM integration process

Analyst Ming-Chi Kuo has echoed other reports that Apple is expected to use a new chip packaging technology in the A20 chip, which will debut in the iPhone 18 next year. His report focuses on suppliers for chip packaging materials, rather than the benefits of the new process. We heard the same from analyst Jeff Pu a couple months ago.

When you buy an iPhone 16 today, the A19 chip inside is a pretty big and complex monolithic “system on a chip.” It’s got the CPU, GPU, Neural Engine, video and audio encoders and decoders, and a bunch of other little stuff all on one big complex piece of silicon with around 30 billion transistors. Many chips are made on a big silicon disk (called a wafer) and then packaged up and cut into individual A19 chips, called “dies.”

But the RAM is not on the same piece of silicon. RAM is typically manufactured using different silicon processes, on different big wafers, cut into their own dies. Then the RAM is combined with the big SoC by connecting the two together using another piece of silicon, called an interposer.

This is done because the manufacturing processes that produces SRAM efficiently is different than what produces logic efficiently. But with a new TSMC technology called “Wafer-Level Multi-Chip Module (WMCM) packaging,” that might all change.

This process will make it possible for Apple to build a big monolithic chip that includes the RAM on the same die as the CPU, GPU, Neural Engine, media encoders, and so on. If the current rumors are correct, this would be 12GB of RAM, but the process doesn’t require any specific amount. Rumors point to the iPhone 18 as the first device to use the new chip, and the iPhone Fold could also be a candidate.

On-die RAM may simplify the manufacturing process, requiring fewer steps than the current RAM-on-interposer setup. But the benefit for users is the potential to have very wide and fast RAM interfaces, making access to RAM almost as fast as a high-level SRAM cache. This could drastically improve performance in situations that are limited by memory bandwidth, such as high-performance 3D graphics or certain AI applications.

It could also allow for better power management, allowing the SoC with integrated RAM to use less power than the current setup with RAM attached on an interposer. This may improve battery life, but battery life is a factor of many different components like the display, wireless radios, storage, and more.